A chip design containing logic circuits supporting built in self test (BIST) has stringent connectivity and timing requirements. When the logic circuits have been placed and routed to meet all functional and timing requirements, including the BIST requirements, the design is considered complete and ready for release to manufacturing. Enhancements to an existing product or a new product based on an existing chip design may be developed once the existing chip design has been validated. To develop the new enhancements or the new product, modifications may be made to the existing chip design, using an engineering change order (ECO). These modifications may require significant changes with the addition of relatively large functional blocks and changes to existing logic functions.
Large-scale modifications to an existing chip design can be exceptionally difficult due to the absence of an automated process to change the existing chip design while satisfying strict connectivity, scan chain length, data transfer requirements of design for test (DFT), and timing requirements of BIST. It is also desirable to mitigate risk and minimize the impact to a current chip database for an existing design when processing an ECO. Prior techniques might require complete DFT redesign, reimplementation, and revalidation of the modified chip. The amount of work using such a prior technique would generally have a negative impact on the design cycle, time to market, and design reuse. In addition, the earlier verified database for the existing chip design, that was verified by the corresponding working silicon, could be completely lost due to the change process for the modifications required during implementing the changes on chip and that would substantially increase risk.